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Paper Reviews and In-Class Discussions

Students must submit a paper review prior to each class where paper discussions take place. During each such class we will discuss two papers for 25 minutes each. Each student will be required to review one of the two papers; assignments will be made ahead of time. In addition, one student from the class will be responsible for leading the class discussion. A sign-up sheet for leading paper discussions will be made available in class.

Format: Paper reviews should be 1 page or less. Please include:

  1. 2-3 sentence summary
  2. 1-2 things you liked about the paper
  3. 1-2 things you didn't like about the paper
  4. 1-2 items of future work or extensions not mentioned by the author
  5. Anything you didn't understand or would like clarified

Deadline: All paper reviews are due by 12:00pm (noon) on the day before class.

Submission: Papers should be submitted to the instructor using a private message on Piazza. When you create a message on Piazza you can choose a folder for the message. Chose the correct “paper#” folder based on the numbering below.

Your paper review will be made available to other class members (particularly the discussion leader) who will aggregate reviews for the discussion. For this reason, do not include sensitive information (such as BYU ID #) in your paper review

Feb 3: HLS Motivations

#1. The future of microprocessors.
#2. A cloud-scale acceration architecture.

Feb 10: HLS Overview

#3. High-Level Synthesis for FPGAs: From Prototyping to Deployment.
#4. LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems.

Feb 17: Scheduling

#5. Force-directed scheduling for the behavioral synthesis of ASICs.
#6. Modulo SDC scheduling with recurrence minimization in high-level synthesis.

Feb 22: Compiler Techniques

#7. The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs.
#8. Helix: Making the Extraction of Thread-Level Parallelism Mainstream.

Mar 3: Bitwidth Analysis

#9. Bitwidth analysis with application to silicon compilation.
#10. Range and bitmask analysis for hardware optimization in high-level synthesis.

Mar 10: Memory Optimizations

#11. Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. A New Approach to Automatic Memory Banking using Trace-Based Address Mining
#12. Memory partitioning and scheduling co-optimization in behavioral synthesis.

Mar 15: Parallelism/Resource Sharing

#13. From software threads to parallel hardware in high-level synthesis for FPGAs.
#14. Multi-pumping for resource reduction in FPGA high-level synthesis.

Mar 24: Design Space Exploration

#15. A genetic algorithm for the design space exploration of datapaths during high-level synthesis.
#16. SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.

Mar 29: Power

#17. Power estimation for high level synthesis.
#18. High-level Synthesis for Low-power Design.

Apr 7: OpenCL

#19. Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms.
#20. Energy Efficient Scientific Computing on FPGAs using OpenCL.

Apr 12: HW/SW Co-Design

#21. Hardware/Software Codesign: The Past, the Present, and Predicting the Future.

papers.txt · Last modified: 2017/03/10 11:56 by jgoeders